When the layers of a multilayer printed board are connected with lines, holes are made on the printed board and the inner walls (side walls) of the holes are plated to create vias. The vias allow connections between the layers.
Incidentally, as a structure of printed board to achieve a higher density of wiring, there is a via division structure in which a via is divided and a plurality of wiring patterns are connected.    [Patent Document 1] Japanese Laid-open Patent Publication No. 08-123839    [Patent Document 2] Japanese Laid-open Patent Publication No. 2000-101241    [Patent Document 3] Japanese Laid-open Patent Publication No. 2000-216513
However, in the above via division structure, an impedance mismatch may occur on the transmission path due to the impedance of the via, causing the quality of signals to deteriorate.